Several basic device architectures exist for constructing image sensor arrays. Two Of these are the frame transfer and line-address architectures. These architectures generally have a plurality of CCD elements arranged in rows and columns. For each CCD photosite well, an additional well separated by a barrier needs to be fabricated adjacent to it for receiving the stored charge. Further, pixel density is decreased by the requirement of channel stops. In certain of these devices, drains are formed in the channel stops to prevent blooming, and this occupies further array area.
Another class of imagers is arranged according to the interline transfer architecture. These devices comprise a plurality of photosites that can be either empty CCD wells or photodiodes. The photosites are separated by columns of CCD elements provided for readout of the signal. The necessity for the CCD columns decreases pixel density. Channel stops and barriers are required since CCD elements are used in the structure, and this further decreases pixel density.
Yet another class of devices uses an X-Y architecture, wherein each cell or element is individually addressed in the X and Y direction in order to read it out. Conventional X-Y architectures include charge injection devices (CIDs), MOS transistor devices and, more recently, charge-modulated transistor devices. In the CID device, two gates are formed, one connected to a column line, and another connected to a row line. CID arrays have long readout leads, and therefore, have a large parasitic capacitance. This in turn lowers the dynamic range of the device because of the kTC noise associated with the long, high-capacitance readout lines. Further, since each cell is required to be separately read out, the readout of an entire row of cells takes a considerable time. The high-density television (HDTV) format requires that the addressing and readout of an image sensor array used in connection therewith be done within a standard 53-5-microsecond period. Thus, if there are 1000 elements in a row of a CID array device that is operated in the HDTV format, each element in the row must be addressed and read in 53.5 nanoseconds. This is very difficult to accomplish because of the RC time constant associated with charging up the readout lines, which in turn limits the size of CID image sensor arrays. Further, the relatively large time necessary to read out the array increases smear.
MOS transistor arrays have the same problems as CID arrays relative to their long, large-capacitance sense lines. In addition, the charge from each address element is not amplified, but is instead read out directly on these sense lines. Pixel density of these device arrays is reduced by the requirement of forming either one or two transistors at each photosite for addressing purposes.
Recently, a charge modulated device has been proposed by T. Nakamura, K. Matsumoto et al. in their article "A New MOS Phototransistor Operating in a Non-Destructive Readout Mode," Japanese Journal of Applied Physics, Vol. 24, No. 5, pp. L323-325 (May, 1985). This proposed sensor array has the same X-Y architecture as the CID and MOS architectures mentioned above, and thus suffers the same dynamic range and speed problems as the other X-Y addressed architectures.
A 53.5 ns readout time is difficult to meet by present polysilicide gate technology if the column sense lines of the array become too long.
X-Y addressed transistor imager pixels known in the art in general -suffer from several other problems. A first drawback of certain conventional transistor imager pixels is that they have a gate region that is completely covered by an overlying, partially transparent or translucent conductor, conventionally fabricated of polysilicon. The presence of this overlying gate conductor reduces the quantum efficiency of the device.
Further, transistor imager element structures recently introduced in the literature modulate the current passing through them rather than sensing a voltage threshold modulation. This current will vary both with the intrinsic threshold voltage of the element producing it and also that element's size. Variations from element to element in these respects therefore produce "pattern noise." The threshold and size parameters of the sensing elements must therefore be tightly controlled; however, this control becomes progressively more difficult as the size of the element decreases.
The long readout time of conventional X-Y approach exacerbates such problems as smearing, blooming and element-to-element charge leakage from unaddressed rows to addressed rows.
A need therefore exists in the industry for a transistor sensor element that has good quantum efficiency, isolates itself with respect to adjacent imaging pixels, produces a modulated voltage signal rather than a current signal, has low pattern noise, and has a sufficiently fast readout for HDTV applications.